1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a metal-oxide semiconductor (MOS) transistor, using an improved ion implantation process.
2. Description of Related Art
A semiconductor device always includes several MOS transistors, which are fabricated in high integration so as to form an integrated circuit (IC) device. The MOS transistors are the fundamental elements of the IC device. Its properties, such as operation speed, determine the performance of the IC device.
FIGS. 1A-1C are cross-sectional views, schematically illustrating a conventional fabrication process of a MOS transistor. In FIG. 1A, a field oxide layer (FOX) 12 serving as an isolation structure is formed on a semiconductor substrate 10. An area of the substrate 10 other than the FOX layer 12 is called an active area, where an MOS transistor 14 is formed. The MOS transistor 14 includes a gate oxide layer 20, a gate 22, and a lightly doped region 16, in which the gate oxide layer 20 and the gate 22 forms together as a gate structure 19. Conventionally, in order to prevent a punch through effect from occurring on the junction, an anti-punch-through implantation is usually performed to form a halo doped region 18 below the lightly doped region 16 by a higher ion energy beam. The dopant type of the halo doped region 18 is opposite to the dopant type doped in the interchangeable source/drain region 16. A dopant conventionally may be viewed as a substance, such as boron, added in small amounts to a pure semiconductor material to alter its conductive properties for use in transistors and diodes.
In FIG. 1B, a thin conformal silicon dioxide layer (not shown) is formed over the substrate 10, and a silicon nitride layer (not shown) is formed on the silicon dioxide layer. An etching back process is performed to remove the silicon nitride layer and the silicon dioxide layer, all of which respectively leave a silicon dioxide remains 24, or called a liner oxide layer 24, and a silicon nitride remains 26 and form together on each side of the gate structure 19 to serve as a sidewall spacer 23. As seen in FIG. 1B, the liner oxide layer 24 extends over the lightly doped region 16. This extension may be thought of as an extension of gate oxide layer 20 that overlaps the lightly doped region 16.
In FIG. 1C, using the FOX layer 12, the gate structure 19 as a mask, an ion implantation process with a higher dosage density is performed to dope an exposed area of the substrate 10 at the lightly doped region 16. After an annealing process, a heavily doped region 28 abutting the lightly doped region 16 and the halo doped region 18 is formed. All of the lightly doped region 16, the heavily doped region 28 and the halo doped region 18 serve together as an interchangeable region of the transistor 14.
In the above descriptions, for a design of a sub-micron IC device, in order to prevent the punch through effect from occurring on the junction, which is the interchangeable source/drain region, the anti-punch-through implantation is usually performed to form the halo doped region 18 below the lightly doped region 16.
Moreover, in order to increase an direct-current (DC) operation speed of the MOS transistor 14 of FIG. 1A, the heavily doped region 28 is necessary to be formed. However, a depletion region usually exists at an interface of the interchangeable source/drain region and the substrate due to, for example, a depletion of electron-holes for P-type substrate. This depletion region behaves like an capacitor and contributes a junction capacitance. The junction capacitance is larger if the depletion region is larger. The depletion region is larger if the dopant density is larger or junction contact area is larger. A higher dopant density also needs a higher dopant density in the halo doped region in order to reduce a short channel effect. Since the heavily doped region 28 carries higher dopant density, it results in a higher junction capacitance. It is natural for an AC circuit that the junction capacitance can reduce an alternative-current (AC) operation speed. In addition, the gate oxide layer also induces an oxide capacitor, which is coupled with the junction capacitor in series. The oxide capacitor increases the junction capacitance and causes a slower AC operation speed.
Furthermore, if the junction capacitance is reduced through a reduction of the junction contact area, the junction depth is usually reduced. This causes a difficult control on the margin of junction.
It is therefore an objective of the present invention to provide an improved method for forming an interchangeable source/drain region. The improved method includes a formation of a low dopant density region below the interchangeable source/drain region so as to reduce a junction capacitance. An AC operation speed is further increased.
It is another an objective of the present invention to provide an improved method for forming an interchangeable source/drain region. The improved method includes a formation of a low dopant density region below the interchangeable source/drain region so as to allow a thicker junction depth to be formed. Thus a margin of the junction can be more easily controlled.
It is still another an objective of the present invention to provide an improved method for forming a spacer on each sidewall of a gate structure. The improved method includes forming a thin liner spacer instead so as to reduce a lateral extension length of the interchangeable source/drain region. The overlap region between the gate structure and the interchangeable source/drain region is therefore reduced so that a less overlapping capacitance can be obtained. An AC operation speed is further increased.
In accordance with the foregoing and other objectives of the present invention, an improved method for fabrication a MOS transistor is provided. The improved method is suitable for a semiconductor substrate having a gate structure. The improved method includes forming a liner spacer on each side of the gate structure. Using the gate structure and the liner spacer as a mask, an ion implantation process with very high beam energy is performed to form a low dopant density region deep inside the substrate. The dopant is a first-type dopant, which is opposite to the substrate. A lightly doped region with the first-type dopant is formed in the low dopant density region on the top portion preferably by ion implantation. An anti-punch-through region having a second-type dopant with a sufficient dopant density is formed between the low dopant density region and the lightly doped region. The second-type dopant is opposite to the first-type dopant so as to prevent a punch-through effect from occurring. A sidewall spacer is formed on the liner spacer, which is on each side of the gate structure. Using the gate structure and the spacers as a mask, an ion implantation process is performed to form a heavily doped region in the substrate on the top portion of the low dopant density region. The heavily doped region is doped with the first-type dopant and has a dopant density higher than the low dopant density region and the lightly doped region. Thus, the junction of the MOS transistor of the invention includes an interchangeable source/drain region, which includes the lightly doped region and the heavily doped region, the anti-punch-through regions and the low dopant density region below these three regions to separate these three regions from the substrate.